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 DATA SHEET
Part No. Package Code No.
AN12969A
UBGA031-W-3030AEA
Publication date: October 2008
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AN12969A Contents
Overview ............................................................................................................................ 3 Features ............................................................................................................................ 3 Applications ........................................................................................................................ 3 Package ............................................................................................................................ 3 ................................................................................................... 4 Type ................................................................................................................................. 3 Application Circuit Example Pin Descriptions .................................................................................................................. 5 Absolute Maximum Ratings .................................................................................................... 7 Operating Supply Voltage Range ............................................................................................ 7 Electrical Characteristics ....................................................................................................... 8 Electrical Characteristics (Reference values for design) ............................................................... 10 Technical Data ................................................................................................................... 12 1. I2C-bus Mode .................................................................................................................... 14 2. Operating temperature guarantee of I2C-Bus control .................................................................. 16 3. Usage note of I2C-bus ............................................................................................................ 16 4. I/O block circuit diagrams and pin function descriptions .............................................................. 17 5. Power supply and logic sequence .......................................................................................... 23 6. Explanation on mainly functions ............................................................................................. 25 7. PD -- Ta diagram .............................................................................................................. 29 Usage Note ........................................................................................................................ 30
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AN12969A
AN12969A
I2C bus control compatible AGC built-in stereo BTL amplifier IC (For driving a piezoelectric speaker)
Overview
AN12969A has a built-in AGC function in a stereo BTL amplifier for driving a piezoelectric speaker to prevent noise at output clip, and has a built-in a charge-pump power supply for driving speaker output amplifiers. And I2C bus control method is applied in switching of each mode like some Standby function is turned ON/OFF.
Features
The piezoelectric speaker can be driven by applying the circuit of high withstand voltage power amplifier. On level in AGC can be selected by controlling I2C bus. Attack and recovery times in AGC can be selected by controlling I2C bus. Resistance and capacitor, which were used for conventional analog AGC aren't needed anymore. I2C is controlled almost in the same way as those of AN12959A. Shut-down function is mounted. Amplifier gain switching The input circuit constructs a bus boost circuit easily and improves the sound quality of the piezoelectric speaker. The supply for speaker output amplifier isn't needed anymore.
Applications
Audio amplifier for mobile, such as a cellular phone
Package
31 pin Plastic Quad 6 Column BGA Package(0.5 mm Pitch)
Type
Silicon Monolithic Bi-CMOS IC
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AN12969A
Application Circuit Example
VBAT = 3.0 V - 4.5 V 2.2 F E5 VBAT VREG_PRED 390 1 F F5 C1N F4 C1P 0.1 F 2.2 F
F2 CPOUT
E6
E4
F3
F1 GND
E1 ROUT_POS
GND_CP F6 GND D3 PREOUT_R D4 1 500 pF 10 k INPUT_R 0.1 F 10 k INPUT_L 0.1 F 10 k FB_R D5 FB_L D6 10 k
Charge
Pump
+14 dB D1 GND_SPR
22
+6 dB / 0 dB Gain Select AGC AGC DET AGC +6 dB / 0 dB Gain Select
+14 dB
C1 ROUT_NEG C2 VCC_SP C3 VREF_SP 1 F B1 LOUT_NEG
22
+14 dB
22
1 500 pF PREOUT_L C5 GND C4 B4 A6 SCL A5 I2C-BUS Control
+14 dB
A1 GND_SPL
VCC A3 1 F
VCC_D A4
2.2 k
2.2 k
0.1 F
1 F
*2 Operate Shutdown
1 F
VREF B2
SDA B5
S.D B3
A2 LOUT_POS
22
VCC_D = 1.7 V - 3.3 V
VCC = 2.7 V - 4.5 V
Diagram of pin names on package bottom face
2.96 mm 0.5 mm 0.31 mm 0.23 mm
GND CP
B3 pin Operate voltage VCC_D = 1.8 V Operate > 1.62 V Shut-down < 0.18 V VCC_D = 2.6 V Operate > 2.34 V Shut-down < 0.26 V F E D C B
Note) This circuit and these circuit constants show an example and do not guarantee the design as a mass-production set. *2 : The threshold voltage at Pin B3 has the VCC_D dependency. *3 : This block diagram is for explaining functions. The part of the block diagram may be omitted, or it may be simplified.
GND ROUT POS GND SPR ROUT NEG VCC SP GND VREF SP SD VCC CP OUT CP OUT C1P C1N
VREG PRED VBAT VBAT PRE OUTR GND GND VCCD FBR PRE OUTL SDA SCL GND FBL
LOUT NEG VREF GND LOUT SPL POS
A
1
2
3
4
5
6
Note) N.C. pin is without a solder ball.
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2.96 mm
AN12969A
Pin Descriptions
Pin No. A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 C1 C2 C3 C4 C5 C6 D1 D2 D3 D4 D5 D6 Pin name GND_SPL LOUT_POS VCC VCC_D SCL GND LOUT_NEG VREF S.D GND SDA N.C. ROUT_NEG VCC_SP VREF_SP GND PREOUT_L N.C. GND_SPR N.C. GND PREOUT_R FB_R FB_L Type Ground Output Power Supply Power Supply Input Ground Output Input Input Ground Input / Output -- Output Power Supply Input Ground Output -- Ground -- Ground Output Input Input Description Grounding (For speaker L-channel) Speaker output L-channel (+) Power supply VCC VCC_D for logic circuit SCL Grounding Speaker output L-channel (-) Reference voltage pin Shut-down pin Grounding SDA N.C. Speaker output R-channel (-) VCC_SP for the circuit of speaker output Reference voltage pin for the circuit of speaker output Grounding First amplifier output L-channel N.C. Grounding (For speaker R-channel) N.C. Grounding First amplifier output R-channel First amplifier negative feedback input R-channel First amplifier negative feedback input L-channel
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AN12969A
Pin Descriptions (continued)
Pin No. E1 E2 E3 E4 E5 E6 F1 F2 F3 F4 F5 F6 Pin name ROUT_POS N.C. N.C. VREG_PRED VBAT VBAT GND CPOUT CPOUT C1P C1N GND_CP Type Output -- -- Output Power Supply Power Supply Ground Output Output Output Output Ground Speaker output R-channel (+) N.C. N.C. VREG capacitor pin for charge pump gate-driver VBAT for Charge-pump VBAT for Charge-pump Grounding Charge-pump output Charge-pump output Charge pump flying capacitor pin (+) Charge pump flying capacitor pin (-) Grounding (For charge-pump) Description
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AN12969A
Absolute Maximum Ratings
A No. 1 2 3 4 5 Parameter Supply voltage Supply current Power dissipation Operating ambient temperature Storage temperature Symbol VCC,VBAT VCC_D ICC PD Topr Tstg Range 5.0 3.6 -- 136 -20 to +70 -55 to +150 Unit V A mW C C Note *1 -- *2 *3
Note) *1 : The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2 : The power dissipation shown is the value at Ta = 70C for the independent (unmounted) IC package with a heat sink. When using this IC, refer to the PD-Ta diagram in the Technical Data and design the heat radiation with sufficient margin so that the allowable value might not be exceeded based on the conditions of power supply voltage, load, and ambient temperature. *3 : Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25C.
Operating supply voltage range
Parameter Symbol VCC Supply voltage range VCC_D VBAT Range 2.7 to 4.5 1.7 to 3.3 3.0to 4.5 V Unit Note *1 *1, *2 *1
Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The I2C bus of this product is designed to correspond to Standard mode(100 Kbps) and Fast mode(400 Kbps) in Philips Corporation I2C specification version 2.1 at VCC_D = 1.7 V to 3.3 V. However, not correspond to High Speed mode ( < 3.4 Mbps).
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AN12969A
Electrical Characteristics
Note) Unless otherwise specified, Ta = 25C2C, VCC = 3.0 V,VCC_D = 1.8 V, VBAT =3.8 V
B No. Circuit Current 1 2 3 4 5 6 7 8 9
Parameter
Symbol
Conditions
Limits Min Typ Max
Unit Note
Circuit current 1A at non-signal Circuit current 2A at non-signal Circuit current 3A at non-signal Circuit current 1B at non-signal Circuit current 2B at non-signal Circuit current 3B at non-signal Circuit current 1C at non-signal Circuit current 2C at non-signal Circuit current 3C at non-signal
IVCC1A IVCC2A IVCC3A IVCC1B IVCC2B IVCC3B IVCC1C IVCC2C IVCC3C
Non-signal, STB = OFF, SP_SAVE = OFF, AGC = ON Non-signal, STB = OFF, SP_SAVE = OFF, AGC = ON Non-signal, STB = OFF, SP_SAVE = OFF, AGC = ON Non-signal, STB = ON, SP_SAVE = ON, AGC = ON Non-signal, STB = ON, SP_SAVE = ON, AGC = ON Non-signal, STB = ON, SP_SAVE = ON, AGC = ON Non-signal, STB = OFF, SP_SAVE = ON, AGC = ON Non-signal, STB = OFF, SP_SAVE = ON, AGC = ON Non-signal, STB = OFF, SP_SAVE = ON, AGC = ON
-- -- -- -- -- -- -- -- --
0.5 28 0.1 0.1 0.1 0.1 0.5 19 0.1
1.0 46 10 1.0 1.0 1.0 1.0 23 10
mA mA A A A A mA mA A
-- -- -- -- -- -- -- -- --
I/O Characteristics 10 11 12 13 SP reference output level SP reference output distortion SP reference output noise voltage Output level at SP Save VSPOL VSPOR THSPOL THSPOR VNSPOL VNSPOR VSSPOL VSSPOR VIN = -26.0 dBV, f = 1 kHz, RL = 100 VIN = -26.0 dBV, f = 1 kHz, RL = 100 , to THD5th Non-Signal using A curve filter VIN = -26.0 dBV, f = 1 kHz, RL = 100 using A curve filter -1.0 -- -- -- 0.0 0.07 -75 -114 1.0 0.5 -68 -90 dBV % dBV dBV -- -- -- --
14
SP AGC output level
VIN = -6.0 dBV, f = 1 kHz, VSPOA1L RL = 100 , VBAT = 4.3 V, VSPOA1R AGC - SELECT = [000]
11.6
12.6
13.6
dBV
--
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AN12969A
Electrical Characteristics (continued)
Note) Unless otherwise specified, Ta = 25C2C, VCC = 3.0 V,VCC_D = 1.8 V, VBAT =3.8 V
B No. I2C interface 15 16
Parameter
Symbol
Conditions
Limits Min Typ Max
Unit
Note
SCL, SDA signal input Low level SCL, SDA signal input High level
VIL VIH
-- -- Open corrector, sync current : 3mA Input voltage 0.1 V to 1.7 V --
-0.5 0.7 x VCC_D 0 -10 0
-- --
0.3 x VCC_D VCC_D + 0.5 0.2 x VCC_D 10 400
V V
-- --
17 18 19
SDA signal output Low Level SCL, SDA signal input current Max. frequency of SCL signal allowable to input
VOL Ii fSCL
-- -- --
V A kHz
-- -- --
The threshold voltage at Pin B3 20 21 Shut-down input Low level Vsdlth Vsdhth -- -- -- 0.9 x VCC_D -- -- 0.1 x VCC_D -- V V -- --
Shut-down input High level
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AN12969A
Electrical Characteristics (Reference values for design)
Note) Unless otherwise specified, Ta = 25C2C, VCC = 3.0 V,VCC_D = 1.8 V, VBAT =3.8 V The characteristics listed below are reference values for design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, Panasonic will respond in good faith to user concerns.
B No. I2C interface 22 23 24 25 26 27 28 29 30 31
Parameter
Symbol
Conditions
Reference values Min Typ Max
Unit
Note
Bus free time between stop and start conditions Setup time of start condition Hold time of start condition Low period of SCL clock High period of SCL clock Rising time of SDA, SCL signal Falling time of SDA, SCL signal Data setup time Data hold time Setup time of stop condition
tBUF tSU;STA tHD;STA tLow tHigh tR tF tSU;DAT tHD;DAT tSU;STO fCP
-- -- -- -- -- -- -- -- -- --
1.3 0.6 0.6 1.3 0.6 -- -- 0.1 0 0.6
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- 0.3 0.3 -- 0.9 --
s s s s s s s s s s MHz
-- -- -- -- -- -- -- -- -- --
Charge pump 32 Oscillation frequency -- -- 1.25 -- --
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AN12969A
Electrical Characteristics (Reference values for design) (Continued)
Note) Unless otherwise specified, Ta = 25C2C, VCC = 3.0 V,VCC_D = 1.8 V, VBAT =3.8 V The characteristics listed below are reference values for design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, Panasonic will respond in good faith to user concerns.
START CONDITION VIHmin
Repeated START STOP CONDITION CONDITION
START CONDITION
SDA
tF tLow tR tSU;DAT tF
(*2)
VILmax(*3) tBUF tR tHD;STA
SCL
tHD;STA tHD;DAT tHigh tSU;STA tSU;STO
Note) 1. The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, we will respond in good faith to user concerns. 2. *1: All values are VIHmin (*2) and VILmax (*3) level standard. *2: VIHmin is the minimum limit of the signal input high level is indicated. *3: VILmax is the maximum limit of the signal input low level is indicated.
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AN12969A
Technical Data
1. I2C-bus Mode 1) Write Mode SDA
SCL
SLAVE ADDRESS SUB ADDRESS DATA ACK ACK STOP CONDITION
START CONDITION
ACK
10110110 B 6
00000001 0 1
10000000 8 0
Example of transmission messages Two transmission messages (i.e. the SCL and SDA) are sent in synchronous serial transmission. The SCL is a clock with fixed frequency. The SDA indicates address data for the control of the reception side, and is sent in parallel in synchronization with the SCL. The data is transmitted in 8-bit, 3 octets (bytes) in principle, where every octet has an acknowledge bit. The following description provides information on the structure of the frame. When the level of the SDA changes to low from high while the level of the SCL is high, the data reception of the receiver will be enabled. When the level of the SDA changes to high from low while the level of the SCL is high, the data reception of the receiver will be aborted. The slave address is a specified one unique to each device. When the address of another device is sent, the reception will be aborted. The sub-address is a specified one unique to each function. Data is information under control. The acknowledge bit is used to enable the master to acknowledge the reception of data for each octet. The master acknowledges the data reception of the receiver by transmitting a high-level signal to the receiver and receiving a low-level signal returned from the receiver as shown by the dotted lines in the above Fig. The communication will be aborted if the low signal is not returned. The SDA will not change when the level of the SCL is high except start or stop conditions are enabled.
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AN12969A
Technical Data (continued)
1. I2C-bus Mode (continued) 1) Write Mode (continued) (a) I2C-bus PROTOCOL Slave address : 10110110 (B6Hex) Format (Normal) S Slave address WA Sub-address A Data byte A P
Stop condition
Start condition
Write Acknowledge bit Mode : 0
(b) Auto increment Auto increment mode (When the data is sent in sequence, the sub-address will change one by one and the data will be input.) Auto increment mode S Slave address WA Sub-address A Data 1 A Data 2 A Data n A P
(c) Initial condition The initial state of the device is not guaranteed. Therefore, the input of 00Hex resister-D0(Note.1) will be absolutely "0", when the power is turned ON. (d) Sub-address Byte and Data Byte Format Subaddress *0Hex MSB D7 GAIN 0 +20 dB 1 +26 dB AGC-ON data bit3 0 (*1,*2) D6 0 (*1) AGC-ON data bit2 0 (*1,*2) D5 0 (*1) AGC-ON data bit1 0 (*1,*2) D4 0 (*1) AGC-REC data bit3 0 (*1,*2) Data byte D3 AGC 0 OFF 1 ON AGC-REC data bit2 0 (*1,*2) D2 SP Save 0 ON 1 OFF AGC-REC data bit1 0 (*1,*2) D1 All Standby 0 ON 1 OFF AGC-ATT data bit2 0 (*1,*2) LSB D0 0 (*1) AGC-ATT data bit1 0 (*1,*2)
*1Hex *2Hex
Note) *1: <00Hex Register> D0, D4, D5, D6 : Always set to "0" D1 : SP and charge-pump standby ON/OFF switch D2 : SP Save ON/OFF switch D3 : AGC ON/OFF switch D7 : GAIN +20 dB / +26 dB selection <01Hex Register> D0, D1: AGC-attack-time selection D2, D3, D4 : AGC-recovery-time selection D5, D6, D7 : AGC-on-level selection <02Hex Register> D0 to D7 : Always set to "0". (test & adjust mode). *2: Please use these bit only Data = "0", because they are used by our company's final test and fine-tuning AGC-on level. Note that Data = "1" is not shut-down mode.
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AN12969A
Technical Data (continued)
1. I2C-bus Mode (continued) 1) Write Mode (continued) (e) AGC-attack-time selection Write 01Hex Register D1 0 0 1 1 D0 0 1 0 1 Attack time 0.5 ms 1 ms 2 ms 4 ms (f) AGC-recovery-time selection Write 01Hex Register D4 0 0 0 0 1 1 D3 0 0 1 1 0 0 D2 0 1 0 1 0 1 Recovery time 1.0 s 1.5 s 2.0 s 3.0 s 4.0 s 6.0 s
(g) AGC-on-level selection at VCC = 3.0 V, VCC_D = 1.8 V, VBAT = 3.8 V *1 Write 01Hex Register D7 0 0 0 0 1 1 1 1 D6 0 0 1 1 0 0 1 1 D5 0 1 0 1 0 1 0 1 AGC On Level 12.6 dBV 13.2 dBV 13.9 dBV 14.5 dBV 15.1 dBV 15.6 dBV 16.1 dBV 16.6 dBV Output (V[p-p]) 12 V[p-p] 13 V[p-p] 14 V[p-p] 15 V[p-p] 16 V[p-p] 17 V[p-p] 18 V[p-p] 19 V[p-p]
Note) *1: At the time of VBAT = 3.1 V, output is clipped, excessive clip in AGC OFF can be prevented.
(h) Amp. gain selection at VCC = 3.0 V, VCC_D = 1.8 V, VBAT = 3.8 V Write 00Hex Register D7 0 1 20 dB 26 dB
Gain
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AN12969A
Technical Data (continued)
1. I2C-bus Mode (continued) 2) Read Mode (a) I2C-bus PROTOCOL Slave address 10110111(B7Hex) Format S Slave address R A Data 0 A Data 1 A Data 2 A P
Read Mode : 1 Note) At the slave address input, it is sequentially output from Data 0. There is no necessity for inputting the sub-address.
(b) Sub-address Byte and Data Byte Format MSB D7
Data 0
Data byte D6 D5 D4 D3 D2 D1
LSB D0
Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address *0Hex *0Hex *0Hex *0Hex *0Hex *0Hex *0Hex *0Hex Latch data D7 Latch data D6 Latch data D5 Latch data D4 Latch data D3 Latch data D2 Latch data D1 Latch data D0 Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address *1Hex *1Hex *1Hex *1Hex *1Hex *1Hex *1Hex *1Hex Latch data D7 Latch data D6 Latch data D5 Latch data D4 Latch data D3 Latch data D2 Latch data D1 Latch data D0 Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address Sub-address *2Hex *2Hex *2Hex *2Hex *2Hex *2Hex *2Hex *2Hex Latch data D7 Latch data D6 Latch data D5 Latch data D4 Latch data D3 Latch data D2 Latch data D1 Latch data D0
Data 1
Data 2
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AN12969A
Technical Data (continued)
2. Operating temperature guarantee of I2C-bus Control The performance in the ambient temperature of operation is guaranteed theoretically in the design at normal temperature (25C) by inspecting it at a speed of the clock that is about 50% earlier regarding the operating temperature guarantee of I2C-bus Control. But the following characteristics are logical values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, Panasonic will respond in good faith to customer concerns.
3. Usage note of I2C-bus 1. The I2C bus of this product is designed to correspond to Standard mode(100 Kbps) and Fast mode(400 Kbps) in Philips Corporation I2C specification version 2.1. However, not correspond to High Speed mode (< 3.4Mbps). 2. This product operate as a slave device in I2C bus system. 3. This product is not confirmed to operate in multi-master bus system and mixing -speed bus system. And this product is not confirmed connectivity to CBUS receiver. If using this product in these mode, please confirm availability to our company. 4. Purchase of Panasonic I2C components conveys a license to use these components in an I2C systems under the Philips I2C patent right on condition that using condition conform to I2C standard specification approved by Philips Corporation.
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AN12969A
Technical Data (continued)
4. I/O block circuit diagram and pin function descriptions
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Pin No. A1
Waveform and voltage GND_SPL
Internal circuit
Impedance
Description
-- DC 0 V
VCC_SP(6.1 V)
--
Ground pin for L-channel speaker output
LOUT_POS A2 DC 2.7 V
4k
20k
A2
Output impedance = Equal to or less than 1
L-channel positive speaker output pin
GND_SPL
VCC A3 3.0 V(typ.) VCC_D A4 1.8 V(typ.)
VCC_D (1.8 V)
--
--
Power supply pin
--
--
Power supply pin for I2C-BUS
SCL
A5
A5 Hi-Z
Input impedance 2 I C-BUS SCL pin = Hi-Z
A6 B4 C4 D3 F1
GND -- DC 0 V -- Ground pin.
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AN12969A
Technical Data (continued)
4. I/O block circuit diagram and pin function descriptions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Pin No.
Waveform and voltage
Internal circuit
VCC_SP(6.1 V)
Impedance
Description
LOUT_NEG B1 DC 2.7 V
4k
20k
B1
Output impedance = Equal to or less than 1
L-channel negative speaker output pin
GND_SPL
VREG(5 V)
VREF B2 DC 2.5 V
B2 150k
The reference voltage terminal for determining DC bias of the input stage of Input impedance a speaker amplifier system. = About 75 k Please connect an external capacitor to remove a ripple.
150k
VCC_D (1.8 V)
S.D B3 Hi-Z
B3
Shut-down mode pin Input impedance Please do not make it open, because the = Hi-Z open S.D pin is not fixed.
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AN12969A
Technical Data (continued)
4. I/O block circuit diagram and pin function descriptions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Pin No.
Waveform and voltage
Internal circuit
Impedance
Description
VCC_D (1.8 V)
SDA
B5
B5 Hi-Z
Input impedance 2 I C-BUS SDA pin = Hi-Z
GND
B6 C6 D2 E2 E3
N.C.
--
--
N.C.
VCC_SP(6.1 V)
ROUT_NEG C1 DC 2.7 V
4k
20k
C1
Output impedance = Equal to or less than 1
R-channel negative speaker output pin
GND_SPR
VCC_SP C2 2xVBAT -- --
Power supply pin for speaker output. Please connect to F2,F3 Pin (CPOUT), and connect an external capacitor to remove a rippule.
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AN12969A
Technical Data (continued)
4. I/O block circuit diagram and pin function descriptions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Pin No.
Waveform and voltage
VCC_SP(6.1 V)
Internal circuit
Impedance
Description
VREF_SP C3 DC 2.7 V
C3
10k 1k 300k
The reference voltage terminal for determining DC bias of the output stage Input impedance of a speaker amplifier system. = About 150 k Please connect an external capacitor to remove a ripple.
300k VREG(5 V)
PREOUT_L C5
C5
DC 2.5 V
Output impedance = Equal to or less than 10
Output terminal of L-channel input amplifier of speaker amplifier system. Please connect external resistance for the gain setting.
GND_SPR D1 DC 0 V
VREG(5 V)
--
--
GND pin for R-channel speaker output
PREOUT_R D4
D4
DC 2.5 V
Output impedance = Equal to or less than 10
Output terminal of R-channel input amplifier of speaker amplifier system. Please connect external resistance for the gain setting.
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AN12969A
Technical Data (continued)
4. I/O block circuit diagram and pin function descriptions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Pin No.
Waveform and voltage
VREG(5 V)
Internal circuit
Impedance
Description
FB_R D5 DC 2.5 V
D5
Input impedance = Hi-Z
Feedback terminal of R-channel input amplifier of speaker amplifier system. The gain of the R-channel input amplifier can be set by connecting an external resistance between Pin D4 and Pin D5.
GND
VREG(5 V)
FB_L D6 DC 2.5 V
D6
Input impedance = Hi-Z
Feedback terminal of L-channel input amplifier of speaker amplifier system. The gain of the L-channel input amplifier can be set by connecting an external resistance between Pin C4 and Pin C5.
GND
VCC_SP(6.1 V)
ROUT_POS
20k
E1 DC 2.7 V
4k
E1
Output impedance = Equal to or less R-channel positive speaker output pin than 1
GND_SPR F2 F3
25
VREG_PRED E4 DC CPOUT * 0.45
25k
75k
E4
Output impedance VREG capacitor pin for charge pump = Equal to or less gate-driver than 1
GND_CP
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AN12969A
Technical Data (continued)
4. I/O block circuit diagram and pin function descriptions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Pin No. E5 E6
Waveform and voltage VBAT
Internal circuit
Impedance
Description
-- 3.8 V(typ.)
VBAT (3.8 V)
--
Power supply pin
F2 F3
CPOUT VBAT*2
F2 F3 F4
1
Charge-pump output pin Please connect an external capacitor to remove a ripple.
F5 GND_CP
VBAT (3.8 V)
C1P
F4
F2 F3
F4 1.25MHz VBAT to CPOUT
F5 GND_CP
1
Charge-pump flying capacitor connect pin.
VBAT (3.8 V)
C1N
F4
F2 F3
F5 1.25MHz GND to VBAT
F5 GND_CP
1
Charge-pump flying capacitor connect pin.
GND_CP F6 DC 0 V -- -- Ground pin for charge-pump.
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AN12969A
Technical Data (continued)
5. Power supply and logic sequence
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
The timing control of power-ON/OFF and each logic according to the procedure below should be recommended for the best pop performance caused in switching.
1) The sequence of the power supply and each logic
Please turn on the power supply first, and then get Standby OFF. The basic procedure at the power-on
VBAT, VCC, VCC_D, SD Power supply
On Off Off
On Off Off On Off Off On 30 ms or more *1 0 ms or more
The power OFF condition. Both the Standby and the SP_Save are in the ON condition. 2. Power ON 3. Standby OFF 4. SP_Save OFF
1.
Standby
On
The basic procedure at the power-off The power ON condition. Both the Standby and the SP_Save are in the OFF condition. 2. SP_Save ON (= Standby ON) 3. Standby ON 4. Power OFF 1.
SP_Save
On
After at least 30 ms has passed after the standby off, please off SP_Save.
Please get Standby On simultaneously with or after SP_Save On.
Note) *1: This IC contains the pre-charge circuit. It is time until each bias is stabilized from Standby Off. It depends for this time on the capacity value linked to a reference voltage terminal (VREF and VREFSP), and the capacity value and resistance linked to an input terminal (IN_R and IN_L). It is a recommendation value in a constant given in the example of an application circuit (block diagram).
2) The sequence of VBAT and VCC and VCC_D This IC does not have a rising and falling order in VBAT and VCC and VCC_D. Rising and falling times of them are recommended 1 ms or more.
On
On Off
VBAT VCC VCC_D
Off
1 ms 1 ms or more
1 ms 1 ms or more
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AN12969A
Technical Data (continued)
5. Power supply and logic sequence (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
3) The sequence of the charge-pump. VBAT, VCC, VCC_D, SD Power supply
Off Off Off On Off On
On
Standby CPOUT *1
On
About 2msec : CPOUT rise time
More than 5msec *2 About 3msec : CPOUT fall time
Note) *1: Charge-pump output CPOUT almost outputs the voltage of VBAT at the time of Standby. Also, it has a built-in discharge circuit of CPOUT pin and operates discharge to CPOUT < (VBAT + 0.9 [V]) at the time of Standby. *2: Please take more than 5msec between Standby Off and next Standby On.
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AN12969A
Technical Data (continued)
6. Explanation on mainly functions
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
6.1 Power supply 1) Power supply for output amplifier The output amplifier operates with voltage applied to VCC_SP. VCC_SP is supplied from built-in charge-pump with output voltage of twice VBAT.
AN12969A output maximum amplitude
VBAT x 2 - 1.3 V (typ.)
2) Power supply for control system The control system operates with power supply applied to VCC pin. (I2C logic, clock generation circuit, etc.) 3) Power supply for signal system The signal system operates with the internal regulator of 5 V. 5 V, reference voltage of the internal regulator is generated from VCC_SP using VCC power supply. By setting signal voltage at 5 V, the dynamic range of the signal can be secured sufficiently. When the gain of the input amplifier is 0 dB, clip occurs at the amplitude of 3 V[p-p] (typ.) in input signal. 4) Power supply for I2C interface I2C interface operates with power supply applied to VCC_D pin. I2C circuit operates with VCC. 5) High voltage at shut-down pin Please use the power supply applied to VCC_D or apply voltage from the outside. Threshold voltage depends on the voltage to VCC_D.
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AN12969A
Technical Data (continued)
6. Explanation on mainly used functions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
6.2 Speaker amplifier
1500 pF 10 k INPUT_L 0.1 F 10 k - +
AGC DET
+14 dB LOUT_NEG BTL : +6 dB
AGC 0 dB +6 dB / 0 dB +14 dB
LOUT_POS
I2C Logic
1) The gain for a speaker amplifier can be adjusted, as the gain for a input amplifier can be set with an external resistance. Input impedance is also set with the external resistance. When the gain for the input amplifier is set at 0 dB, the total gain for the speaker amplifier is +26 dB or +20 dB (It can be selected with I2C). When the external resistance for the input amplifier is assumed as R1, R2,
R2
Gain = 20 log(R2 / R1) Zin = R1
R1 - +
In case of R1 = 10 k, R2 = 10 k with the constants in the above fig, the gain for the input amplifier is 0 dB and impedance is 10 k. During operation, keep the voltage of R1 and R2 at more than 5 k. 2) With an external capacity added to the input amplifier, LPF, which removes an unwanted high frequency element, can be constructed.
C2
When external resistance is assumed as R2, capacity as C2, fc = 1 / (2 x R2 x C2)
R2 - +
In case of R2 = 10 k, C2 = 1500 pF with the constants in the above fig, Cut-off frequency, fc is 10.6 kHz.
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AN12969A
Technical Data (continued)
6. Explanation on mainly used functions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
6.2 Speaker amplifier (continued) 3) With the smaller capacity of the input AC coupling capacitor, HPF, which removes unwanted low frequency element, can be constructed. When input resistance is assumed as R1, and AC coupling capacitor as C1, fc = 1 / (2 x R1 x C1)
C1 0.1 F R1 - + R2
In case of R1 = 10 k, C1 = 0.1 F, cut-off frequency, fc is 160 Hz. In case of R1 = 10 k, C1 = 0.022 F, cut-of frequency, fc is 720 Hz.
4) Bus Boost circuit can be constructed by adding capacity (RBB) and resistance (CBB) to the input amplifier.
The frequency to increase 3 dB is assumed as fo
Cf
fo = Bus Boost Gain Ao =
1 / (2 x x Rf x CBB) 20 log ((Rf + RBB) / Rf) 20 log ((Rf + RBB) / Rin)
CIN RIN Rf
RBB
CBB - +
6.3 Protection circuit for speaker amplifier 1) Thermal protection circuit The thermal protection circuit operates at the Tj of approximately 150C. The thermal protection circuit is reset automatically when the temperature drops. 2) Output pin short protection circuit Output pin-power supply line short protection Output-to-output pin short protection Output pin-GND line short protection If short-circuit is no longer detected, it will return automatically.
Note) Operation is not guaranteed although the protection circuit is built in. Moreover, hundred percent inspection is not guaranteed.
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AN12969A
Technical Data (continued)
6. Explanation on mainly used functions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
6.4 Cautions 1) Cautions about AGC Signal output in the input amplifier is detected and converted to forward current. Compared this forward current with reference voltage, if the forward current is larger, AGC turns ON. When the frequency band of the speaker is narrower than that of the amplifier. If maximum input is made in low frequency band, AGC operates to decrease volume. Namely, low sound part is not heard from a speaker, but AGC reacts to low sound part to turn down the volume. Please carefully design so that the frequency bands is synchronized between the speaker and amplifier.
Note) Frequency characteristics should be set not only for the speaker, but in the built-in condition
The below Graph shows when the values of resistance and capacity are changed.
Frequency Characteristics
VccSP=9V Vin=-22dBV AGC OFF
15 10 Output level BV) 5 0 -5 -10 -15 0.01
Cin=0.1uF Cf=1500pF Rin=10K RF=10K CBB=0 RBB=0 Cin=0.039uF Cf=1500pF Rin=10K RF=5.6K CBB=0.015uF RBB=10K
0.1
1 Input Frequency (kHz)
10
100
2) Cautions about shut-down with SD pin During normal operation, when a shut-down pin is turned Low directly, shock noise comes out. As SP_Save is set in mute, first turn ON SP_Save, and then turn ON Standby to stop operation. Finally, set shut-down pin to Low.
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AN12969A
Technical Data (continued) 7. PD -- Ta diagram
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AN12969A
Usage Notes
1. This IC is intended to be used for general electronic equipment [cellular phones]. Consult our sales staff in advance for information on the following applications: Special applications in which exceptional quality and reliability are required, or if the failure or malfunction of this IC may directly jeopardize life or harm the human body. Any applications other than the standard applications intended. (1) Space appliance (such as artificial satellite, and rocket) (2) Traffic control equipment (such as for automobile, airplane, train, and ship) (3) Medical equipment for life support (4) Submarine transponder (5) Control equipment for power plant (6) Disaster prevention and security device (7) Weapon (8) Others : Applications of which reliability equivalent to (1) to (7) is required 2. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it might smoke or ignite. 3. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. In addition, refer to the Pin Description for the pin configuration. 4. Perform a visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as a solderbridge between the pins of the semiconductor device. Also, perform a full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI during transportation. 5. Take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as output pinVCC short (Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin short (load short) . And, safety measures such as an installation of fuses are recommended because the extent of the above-mentioned damage and smoke emission will depend on the current capability of the power supply. 6. When using the LSI for new models, verify the safety including the long-term reliability for each product. 7. When the application system is designed by using this LSI, be sure to confirm notes in this book. Be sure to read the notes to descriptions and the usage notes in the book. 8. Please carry out the thermal design with sufficient margin such that the power dissipation will not be exceeded, based on the conditions of power supply, load and surrounding temperature. Although indicated also in the column of the maximum rating, the maximum rating becomes an instant and the marginal value which must not exceed. It sufficiently evaluates, and I use-wish-do so that it may not exceed certainly. Moreover, don't impress neither voltage nor current to PIN which is not indicated. It may destroy in both cases. 9. Please do not make it open, because the open SD pin (Pin B3) is not fixed.
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Request for your special attention and precautions in using the technical information and semiconductors described in this book
(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: - Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. - Any applications other than the standard applications intended. (4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20080805


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